Recently, concern over the limit of scaling of a NOR type flash memory for code storage having a capability of random access, is increasing.
According to the technology prediction by ITRS (International Technology Roadmap for Semiconductors) in 2004, even in 2018 when 20 nm semiconductor process technology is predicted to be utilized, it is said to be difficult to realize gate lengths of 130 nm for memory cells of a NOR type flash memory.
One of the main reasons why gate lengths of a NOR type flash memory can not scale is that Channel Hot Electron (CHE) injection is used for writing operations. In order to generate Channel Hot Electron efficiently, a relatively large potential difference is required, which is not less than a barrier voltage of tunnel insulating layer (silicon oxide layer), across a source and a drain of a memory cell. Due to a relatively large depletion layer formed from the drain toward the source of the memory cell caused by the potential difference, scaling of gate lengths will cause problems such that the drain and the source will be connected by the depletion layer (punch through) and generation of Hot Electrons will be prevented.
In order to deal with the problem noted above, a reduction in the potential difference Vds across a source and a drain by using materials for tunnel insulating layers which have lower barrier voltages than that of silicon oxide layer is proposed (see Patent Document No. 1). Furthermore, a NOR type flash memory which applies a method for writing operation other than Channel Hot Electron Injection is also proposed (see Patent Document No. 2). Patent Document No. 1: Japanese Patent Publication 2001-237330, Patent Document No. 2: Japanese Patent Publication H09-8153.